Sr. Staff Engineer, ASIC Design Automation - CAD
Ayar Labs
Design
San Jose, CA, USA
USD 170k-223k / year
Posted on Jan 23, 2026
| Position: Sr. Staff Engineer, ASIC Design Automation - CAD | ||
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| Job Id: 533 | ||
| # of Openings: 0 | ||
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| Sr. Staff Engineer, ASIC Design Automation - CAD Location: San Jose (on-site) We are looking for an expert Chip Design Automation Engineer to architect and maintain the design automation and methodologies for our high-performance ASIC/SoC team. In this role, you will lead the definition and deployment of automated design flows for complex ASIC/SoC that integrate digital logic, custom analog circuits, and photonics components in leading-edge process nodes. As a Senior Staff Design Automation Engineer, you will lead the development of new automation capabilities, optimizing existing methodologies, bridging the gap between EDA tools and the physical design team, and problem-solving to ensure smooth tape-outs. Key Responsibilities
Basic Qualifications
Preferred Qualifications
Salary range: $170,000 - $223,000 NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers. About Ayar Labs: At Ayar Labs we’re about to revolutionize computing by moving data with light. We’re unleashing processing power for artificial intelligence, high performance computing, cloud and telecommunications by removing the bottlenecks created by today’s electrical I/O -- making it possible to continue scaling computing system performance. Ayar Labs is the first to deliver an optical I/O solution that combines in-package optical I/O chiplets and multi-wavelength remote light sources to replace traditional electrical I/O. This silicon photonics-based I/O solution enables chips to communicate with each other from millimeters to kilometers, to deliver orders of magnitude improvements in latency, bandwidth density, and power consumption. With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work. We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities. Resources: Executives from Intel and GLOBALFOUNDRIES share their thoughts on Ayar Labs and the promise of in-package optical I/O (video) Ayar Labs in the News and Recent announcements LinkedIn and Twitter Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply. | ||
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